1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to electrical power consumption by memory arrays such as static random access memory. The present invention is directed to a method and device for conserving power required by restore operations for the memory array.
2. Description of the Prior Art
Conventional computers use several pieces of interconnected hardware, including input/output devices for the user interface (such as a keyboard and display), a permanent storage device (such as a magnetic or optical disk), a temporary memory device (such as random access memory or RAM), and a central processing unit (CPU or processor) which accesses the permanent storage and temporary memory when carrying out program instructions. The present invention relates to power consumption by these devices, particularly by temporary memory devices such as RAM, and execution units in the CPU, such as an arithmetic logic unit.
There are basically three types of RAM: dynamic RAM, static RAM, and pseudo-static RAM. Dynamic RAM stores data in capacitors, that is, it can hold data for only a few milliseconds, so DRAM is typically refreshed (precharged) using external refresh circuitry. Pseudo-static RAM is like DRAM with internal refresh circuitry. Static RAM is a read-write memory array whose storage cells are typically made up of four or six transistors forming flip-flop elements that indefinitely remain in a given binary state (i.e., 1 or 0, corresponding respectively to high or low voltage states) until the information in the cell is intentionally changed, or the power to the memory circuit is shut off, so this memory does not need to be regularly refreshed. It is only necessary to restore (electrically precharge) the SRAM array after or before each evaluation (read or write operation). In a traditional (sense amplifier) memory array, the complete array is restored even though only a small segment of the array is being accessed, resulting in excess power consumption by the array. In addition, the entire array is restored every clock cycle or by some other form of periodic signal and will therefore be restored even if the array is idle (no read/write). Although power considerations are not significant for mainframe or desktop computers, there is a continual attempt to reduce overall power consumption in portable computers that often run on batteries.
In some prior art SRAM designs such as those referred to as a clocked dynamic array, the memory array is broken into groups of "bit lines." See, e.g., U.S. Pat. Nos. 4,972,377 and 5,191,554. In this way, only the group containing the memory location to be accessed is required to be restored. If such a scheme were employed, it would conserve power. These prior designs still require the entire array, i.e., all groups of bit lines, to be restored every clock cycle even if the array is idle (no read or write operations), and the SRAM is usually not accessed every cycle (e.g., a level 2 cache), so this requires additional, unneeded power. It would, therefore, be desirable to devise a method of reducing power consumption by conditionally restoring only the accessed segments of static RAM. It would be further advantageous if the method were also applicable to other circuit functions in the computer system, such as execution units in the CPU.